NeuralPeak · Neural Processing Silicon About · Est. 2021
About / Est. 2021

We Build the Silicon Other People’s Models Run On

NeuralPeak is a semiconductor company. That is a narrow, expensive, and mostly unglamorous business — we are fine with that.

Founded 2021 Discipline silicon + compilers

1. Origin

NeuralPeak was founded in 2021 by three engineers who had each spent a decade on opposite sides of the same problem — one in physical design, one in memory systems, one in compilers. The observation was not new: neural inference at the edge is memory-bound, and general-purpose silicon spends most of its die on the wrong thing.

What the three of them shared was a conviction that the right answer was a purpose-built part with an unusual amount of SRAM, paired with a compiler that treated the memory hierarchy as the resource to be scheduled — not an afterthought to the arithmetic.

We did not start with a pitch deck. We started with a floorplan.

Five years later that floorplan is NP-1 Apex. The company remains small, the toolchain remains ours, and the work remains the same: make on-device inference faster by moving less data, not by adding more transistors.

2. Timeline

2021

Founded

Three founders. A floorplan, a compiler prototype, and a thesis about SRAM.

2022

Architecture defined

NP-1 architecture locked: 16-PE array, three-tier memory, 2-D mesh NoC.

2023

RTL complete

Cycle-accurate simulator (the future peaksim) runs internal workloads.

2024

Tape-out

NP-1 Apex released to the foundry; OSAT and packaging partnerships secured.

2025

Evaluation opens

EVK-1 announced; design partner program opens under mutual NDA.

2026

First silicon

NP-1 boots; NP-2 Crest reaches general availability; PeakStack 3.x.

3. Team

Kai Andersson
Kai Andersson
Co-founder · CEO

Physical design. Owns the tape-out, the foundry relationship, and every word on the datasheet.

Mara Reyes
Mara Reyes
Co-founder · Chief Architect

Memory systems. Designed the three-tier hierarchy and argues about bandwidth in the comments.

David Park
David Park
Co-founder · Compiler Lead

PeakStack. Believes the compiler, not the die, is where performance actually happens.

Lena Novak
Lena Novak
VP Silicon Engineering

Runs the PE microarchitecture and the bring-up lab where first silicon came alive.

Taro Yamada
Taro Yamada
Quantization Lead

INT4 / FP4 / FP8 methodology and the accuracy budget. Publishes the failure cases.

Isabelle Dubois
Isabelle Dubois
Head of Ecosystem

Design partner program and evaluation kits. Translates between silicon and customers.

4. How we operate

The number has conditions

No benchmark figure without its methodology. If you cannot reproduce it, it is not a number — it is a rumor.

A datasheet, not a slogan

We sell silicon to engineers. The copy is written for the person reading the register map at 2 a.m., not the ad agency.

Gated, not gatekept

Whitepapers sit behind an NDA because they describe real silicon — not because we want your email address. Apply; the answer is usually yes.

5. Contact

Design partners

Evaluation kits, NDA, and design-in support.

[email protected]

Press

For reporting on the silicon and the benchmarks.

[email protected]

Careers

Physical design, memory systems, and compiler roles.

[email protected]