Every figure here is measured, not modeled, and carries the conditions that produced it. We publish methodology so the numbers can be reproduced or contested — the two things a benchmark should survive.
Toolchain PeakStack 3.2Samples median of 1,000 runsAmbient 25 °C
1. Throughput vs. batch
ResNet-50, INT8. Throughput saturates as batch grows and the MAC array stays full; the knee is where latency starts to dominate the calculation.
ResNet-50 · INT8 · images/second
median of 1,000 · 25 °C · log-x axis
Figure 1. ResNet-50 INT8 throughput vs. batch size. NP-1 saturates at ~48,000 img/s (batch 64); NP-2 at ~12,000 img/s.
Latency vs. batch · NP-1
ResNet-50 · INT8 · microseconds · batch 1–64
Figure 2. NP-1 latency vs. batch (ResNet-50, INT8): 310 µs at batch 1 rising to 1,333 µs at batch 64.
2. Energy efficiency
TOPS per watt at nominal voltage, measured at full INT8 utilization. The low-power part wins this chart by design — the flagship trades efficiency headroom for raw throughput.
INT8 · TOPS/W · sustained
throughput ÷ measured rail power · typical envelope
NP-4 Ridge
6.7 TOPS/W
NP-2 Crest
6.4 TOPS/W
NP-1 Apex
6.0 TOPS/W
Figure 3. Sustained INT8 energy efficiency, TOPS per watt.
3. Reference results
A fixed set of models across all three parts, so one number maps to one configuration. FP4/INT4 rows use weight-only quantization unless noted.
Workload
Metric
NP-1 Apex
NP-2 Crest
NP-4 Ridge
ResNet-50INT8 · batch 1
latency
310 µs
980 µs
6.9 ms
ResNet-50INT8 · batch 64
throughput
48,000 img/s
12,000 img/s
1,800 img/s
YOLOv8nINT8 · batch 1
throughput
1,650 fps
420 fps
55 fps
Llama-3-8BINT4 · decode
tokens/s
180 tok/s
55 tok/s
8 tok/s
Llama-3-8BINT4 · prefill
tokens/s
12,400 tok/s
3,900 tok/s
620 tok/s
BERT-baseINT8 · batch 32
sequences/s
21,000 seq/s
5,300 seq/s
800 seq/s
NP-4 rows are pre-silicon targets. NP-1/NP-2 measured on engineering silicon.
4. Methodology
What was measured, on what, with which software. Reproducibility is the point.
Hardware under test
NP-1
Engineering silicon, rev 1.2, 85 W typical envelope, FC-BGA on reference board
NP-2
General availability, rev 1.0, 20 W typical envelope
NP-4
Pre-silicon — RTL simulation, not physical measurement
Software
Toolchain
PeakStack 3.2, default scheduling passes
Model source
ONNX export; FP4/INT4 via PeakStack quantizer (weight-only, no retrain)
Runtime
PeakStack runtime, host CPU running at stock clocks
Measurement protocol
Warm-up
100 iterations, discarded
Samples
1,000 iterations, median reported (not mean — rejects outliers)
Ambient
25 °C, forced-air reference thermal
Power
Measured at the core rail, not estimated from TDP
What we do not report
Peak MAC-rate
Not a workload; excluded
Unquantized FP32
Not a supported precision on the array; excluded
Extrapolated figures
Every number maps to a run; no scaled estimates
Interpretation note: these are internal measurements on our silicon and our toolchain. Your results will differ by model, precision, batch, and thermal design. If a figure looks wrong, the methodology above is the place to start — and we would rather you contest it than repeat it.