Silicon / Datasheets

Product Datasheets — One Instruction Set

All NeuralPeak parts share the same ISA and the PeakStack toolchain — a model that runs on NP-4 runs on NP-1 unchanged. Values are framed up to (peak, at nominal voltage) or typical (measured on engineering silicon).

Documents NP1-DS-001 · NP2-DS-002 · NP4-DS-004 Framing up-to / typical

1. Line summary

Parameter	NP-1 Apex	NP-2 Crest	NP-4 Ridge
INT8 (dense)	512 TOPS	128 TOPS	8 TOPS
FP16 / BF16	256 TFLOPS	64 TFLOPS	4 TFLOPS
FP4 / INT4	1,024 TOPS	256 TOPS	16 TOPS
On-chip SRAM	96 MB	32 MB	4 MB
External memory	LPDDR5X · 256 GB/s	LPDDR5 · 128 GB/s	QSPI/OSPI flash
Host interface	PCIe Gen5 x16	PCIe Gen4 x8	— (embedded)
Power (typical)	85 W	20 W	1.2 W
Process	4 nm	6 nm	12 nm
Package	45×45 mm FC-BGA	21×21 mm FC-BGA	12×12 mm QFN-88

2. NP-1 “Apex” — flagship edge accelerator

NP-1 · Apex Doc No. NP1-DS-001 · Rev 1.2 · 2026-08 Engineering silicon

Flagship edge accelerator

4 nm · 45×45 mm FC-BGA · 2,116 balls

For sustained multi-model inference at the edge: vision plus a resident LLM on a single part, with no host offload.

Compute

INT8 throughput	512TOPS UP TO
FP16 / BF16	256TFLOPS UP TO
FP8	512TFLOPS UP TO
FP4 / INT4 (dense)	1,024TOPS UP TO
Structured sparsity	2:4 · up to 2× on INT8 / FP8 / FP4

Memory

On-chip SRAM	96MB80 MB global (16 banks) + 16 MB tile (1 MB × 16 PE)
Global SRAM bandwidth	2.0TB/s UP TO~12 TB/s aggregate across the 16 tile-SRAM blocks
External memory	LPDDR5X · 256GB/s · up to 64 GB

Interfaces & PHY

Host	PCIe Gen5 x16 · up to 128 GT/s
Memory PHY	2× 32-bit LPDDR5X · 8,533 Mbps
Management	I2C · SPI · UART

Power & thermal

Power	85W TYP · 120W maxmeasured at 512 INT8 TOPS, ResNet-50
Supply rails	0.8 V core · 1.1 V I/O
Junction temperature	−40 to +85 °C (industrial)

Package

Process	4 nm
Package	45×45 mm FC-BGA · 2,116 balls · 0.5 mm pitch

Conditions: peak figures at nominal voltage, 25 °C, PeakStack 3.2. Typical power at sustained full utilization. Specifications are preliminary and may change before production release. NP-1 is in pre-production sampling; full electrical characteristics and reliability report available to design partners.

3. NP-2 “Crest” — mid-range, 20 W typical

NP-2 · Crest Doc No. NP2-DS-002 · Rev 1.0 · 2026-06 General availability

Mid-range, 20 W typical

6 nm · 21×21 mm FC-BGA · 700 balls

For camera-adjacent and gateway inference where the power budget is fixed and the host is a single board, not a rack.

Compute

INT8 throughput	128TOPS UP TO
FP16 / BF16	64TFLOPS UP TO
FP8	128TFLOPS UP TO
FP4 / INT4 (dense)	256TOPS UP TO
Structured sparsity	2:4 · up to 2× on INT8 / FP8 / FP4

Memory

On-chip SRAM	32MB · 8 banks
Aggregate on-chip bandwidth	512GB/s UP TO
External memory	LPDDR5 · 128GB/s · up to 16 GB

Interfaces & PHY

Host	PCIe Gen4 x8 · up to 64 GT/s
Memory PHY	1× 32-bit LPDDR5 · 6,400 Mbps
Management	I2C · SPI · UART

Power & thermal

Power	20W TYP · 30W max
Junction temperature	−40 to +85 °C (industrial)

Package

Process	6 nm
Package	21×21 mm FC-BGA · 700 balls · 0.5 mm pitch

Conditions: peak figures at nominal voltage, 25 °C, PeakStack 3.2. NP-2 is generally available in commercial and industrial grades. Full reliability and packaging addendum available to design partners.

4. NP-4 “Ridge” — ultra-low-power MCU-class

NP-4 · Ridge Doc No. NP4-DS-004 · Rev 0.9 · 2026-02 Pre-silicon target

Ultra-low-power MCU-class

12 nm · 12×12 mm QFN-88 · 0.5 mm pitch

A neural coprocessor next to an MCU — keyword spotting, anomaly detection, and sensor fusion on a coin-cell budget.

Compute

INT8 throughput	8TOPS UP TO
FP16 / BF16	4TFLOPS UP TO
FP4 / INT4 (dense)	16TOPS UP TO
Structured sparsity	2:4 · up to 2× on INT8

Memory

On-chip SRAM	4MB · 2 banks
Aggregate on-chip bandwidth	128GB/s UP TO
External memory	QSPI / OSPI flash (weight storage) · no DRAM

Interfaces

Host	— embedded coprocessor
Peripheral	SPI · I2C · UART · USB 2.0 · GPIO

Power & thermal

Power	1.2W TYP · 2.5W max
Junction temperature	−40 to +105 °C

Package

Process	12 nm
Package	12×12 mm QFN-88 · 0.5 mm pitch

Conditions: NP-4 is pre-silicon; figures are simulation targets and will be confirmed on first silicon. Register as a design partner for early-access die and the bring-up SDK.